I am currently a Senior Applications Engineer in the Xilinx University Program in the EMEA region. I am based in Xilinx Ireland, Dublin. I hold an Electronic Engineer degree from Universidad Nacional de San Juan. I also hold a PhD from the Universidad Autónoma de Madrid. My research areas focus on Network monitorisation using FPGA, which can be active or passive depending on the application. Algorithm acceleration, High-Level Synthesis, among many others. I was able to do an academic visit to the Sytems Group of the ETH Zürich in 2018, where I scale up the throughput of an open-source FPGA TCP/IP stack implementation, the result of such work is Limago. I also did an internship at Xilinx Research Labs in Dublin in 2019, where I worked with Michaela Blott and Giulio Gambardella.
2020
2019
“Demonstration of 100 Gbit/s Active Measurements in Dynamically Provisioned Optical Paths”, Jorge E. López De Vergara, Mario Ruiz, Lluís Grifre, Marc Ruiz, Luis Vaquero, José Fernando Zazo, Sergio López-Buedo, Oscar González de Dios and Luis Velasco. The 45th European Conference on Optical Communication (ECOC). Paper
“Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack”, Mario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso and Sergio López-Buedo. In 2019 29th International Conference on Field Programmable Logic and Applications (FPL). Slides
“Towards 100 GbE FPGA-Based Flow Monitoring”, Tobías Alonso, Mario Ruiz, Gustavo Sutter, Sergio López-Buedo and Jorge E. López De Vergara. In 2019 X Southern Conference on Programmable Logic (SPL), pp. 9-16. IEEE, 2019.
2018
“FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks”, Gustavo Sutter, Mario Ruiz, Sergio López-Buedo, and Gustavo Alonso. In 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-6. IEEE, 2018.
“Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip”, Tobías Alonso, Mario Ruiz, Ángel López García-Arias, Gustavo Sutter and Jorge E. López de Vergara. In 2018 28th International Conference on Field Programmable Logic and Applications (FPL), pp. 355-3554. IEEE, 2018. Paper
2017
2016
“FPGA-based Encrypted Network Traffic Identification at 100 Gbit/s”, Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, and Jorge E. López de Vergara. In 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-6. IEEE, 2016.
“Harnessing Programmable SoCs to Develop Cost-effective Network Quality Monitoring Devices”, Mario Ruiz, Javier Ramos, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara and Cristian Sisterna. In 2016 26th International Conference on Field Programmable Logic and Applications (FPL), pp. 1-4. IEEE, 2016.
“Accurate and Affordable Packet-Train Testing Systems for Multi-Gigabit-per-Second Networks”, Mario Ruiz, Javier Ramos, Gustavo Sutter, Jorge E. López de Vergara, Sergio López-Buedo, and Javier Aracil. IEEE Communications Magazine 54, no. 3 (2016): 80-87.
2015